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Introduction

This is the first OpenAMP tutorial demonstrating uC/OS to uC/OS communication on the Zynq-7000 between both ARM cores. This is the easiest configuration to setup and can be done with the pre-defined hardware of the Xilinx SDK or your custom hardware exported from Vivado.

This tutorial assumes that the uC/OS BSP is already installed. For basic information on installation and usage see the Zynq-7000 tutorial.

Software Requirements

  1. A suitable Vivado Design Suite is required for this tutorial. The WebPACK edition can be used if your board is supported.
  2. The µC/OS BSP. The BSP is distributed with the full source code of µC/OS-III for evaluation purpose. See installation instructions.

AMP Setup

The AMP setup used in this tutorial uses the Zynq-7000 PS core 0 as a master running the uC/OS RTOS. Core 1 is configured as a slave processor. Communication between both processors requires three different shared memory region. Namely the transmit and receive vrings as well as a shared memory region for control information. The transmit and receive rings can and should usually be located in cacheable main memory for maximum performance. The shared memory region, called SHMEM in the configuration must be located in coherent memory. All of the main memory of the ARM cores of the Zynq-7000 are coherent by default and we'll place the SHMEM region in main memory.

Boot sequence

When initializing an AMP system using uC/OS as a master the slave processor is expected to boot on it's own. The remoteproc framework should only be used from a Linux master starting a uC/OS slave. This AMP startup method allows for easier debugging and a more robust boot sequence.

Software Setup

First you will have to create the project and BSPs for both cores. The uC/OS BSP comes with pre-defined templates for master and slave configuration of the Zynq-7000 greatly simplifying the initial setup.

Step 1. Create the master project

To create a master project from the template use the File->New->Application Project menu option. From there, type a name for the project, select your hardware platform and choose "ucos" as the OS Platform. Make sure that the PS7 core 0 is selected.

 

 
Figure - Master Project Create Wizard

 

Click the Next button to select an application template. From there select the "Micrium OpenAMP Master Project".

 

 
Figure - Master Project Application Template Wizard

 

Then click finish to generate the project and BSP.

 

To view the demonstration output you will need to select a UART to print messages. This can be done from the BSP configuration panel, in the "ucos" category, expand GENERAL CONFIGURATION and select a uart for the STDIN_OUT field.

 

 
Figure - Master Project Application Template Wizard

 

Step 2. Create the slave project

The same method can be used to create the slave project. From the use the File->New->Application Project menu option again. This time make sure to select core 1.

 

 
Figure - Slave Project Create Wizard

 

Click Next and select the "Micrium OpenAMP Slave Project".

 

 
Figure - Slave Project Application Template Wizard

 

Step 3. AMP configuration

You now have in your work space two project, one master project for core 0 and a slave project for core 1. The default configuration should work by default for this setup but this section briefly cover it for future reference.

Opening the ucos_openamp configuration panel will display the current OpenAMP configuration. Of interest are the MASTER CONFIGURATION and ZYNQ AMP CORE 0 & 1 as seen in the screenshot.

Figure - OpenAMP Configuration Panel

 

In this configuration, core 0 and core 1 are assigned ID 0 and 1 respectively. The shared memory and vring addresses are located in main memory. and interrupt ID 14 and 15 are used for signaling between the two cores. Note that the vring addresses and size only need to be defined for the slave, but the SHMEM should be the same for both master and slave.

Step 4. Debug configuration

When debugging it's recommended to load both cores at the same time since the debugger will start core 0 and 1 at startup.

 

Start by creating a new debug configuration for the master application.

 

 
Figure - Debug Configuration

 

In the application tab the master application should be loaded into core 0 as usual.

 

 
Figure - Master Debug Configuration

 

Then select the ps7_cortexa9_1 core to load the slave application into core 1. Check the "Download application" checkbox.

 

 
Figure - Slave Debug Configuration

 

Step 5. Loading and running

First connect the terminal output of the board and then open a terminal connection from the SDK.

 

 
Figure - Slave Debug Configuration

 

Load the application onto the target. After loading the debugger should be halted with both core 0 and 1 stopped at the beginning of the main function.

 

 
Figure - Debug Window

 

Now it's time to run the demonstration. Press the continue button on both cores starting with core 0. The terminal should print the status of the demo.

 

 
Figure - Terminal Output
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